The server is under maintenance between 08:00 to 12:00 (GMT+08:00), and please visit later.
We apologize for any inconvenience caused
Login  | Sign Up  |  Oriprobe Inc. Feed
China/Asia On Demand
Journal Articles
Laws/Policies/Regulations
Companies/Products
Bookmark and Share
Design and realization of serial cascaded decoder based on HDTV system
Author(s): 
Pages: 39-41
Year: Issue:  4
Journal: TV ENGINEERING

Keyword:  HDTV串行级联码RS码Viterbi译码FPGA;
Abstract: 通过对串行级联码编译码原理的研究分析,结合串行级联码在通信系统中的纠错性能仿真,从硬件实现的角度,提出了串行级联编译码器的总体实现方案.最后基于FPGA电路实现了串行级联的译码,并通过了可编程器件的验证,同时给出了在Quartus环境下的仿真波形.
Related Articles
No related articles found