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Design of DDR3 Controller Based on H.264 Encoder
Author(s): 
Pages: 89-92
Year: Issue:  23
Journal: Video Engineering

Keyword:  asynchronous transmissionbandwidth;
Abstract: 在分析H.264编码过程中对存储器带宽需求的基础上,设计了一种高效、通用的DDR3控制器.结合H.264编码器IP核与外存之间的地址映射关系和DDR3双倍速率传输的特性,采用减少DDR3的行、列切换及设计异步控制逻辑单元等方法缩减H.264编码器对外存的读写操作时间.该结构可使DDR3运行在比编码器更高的频率上,并保证跨时钟域间的数据同步,进一步提高外部存储器的带宽利用率.整个系统通过EDA工具进行仿真调试,并在Altera公司StratixⅣ系列FPGA开发板上进行验证.
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