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Design of Sigma-delta Modulator in Fractional-N PLL Frequency Synthesizer
Pages: 55-58
Year: Issue:  17
Journal: Video Engineering

Abstract: 介绍了一种应用于小数N分频频率综合器的工作于20 MHz的Sigma-delta调制器的设计,采用3个一阶电路级联的MASH1-1-1结构的噪声整形电路.电路设计利用Verilog硬件描述语言进行描述,在modelSim SE 6.2b中通过了功能仿真,并在XUP Virtex-Ⅱ Pro FPGA开发板上进行了验证,最终采用TSMC 0.13 μm CMOS工艺,完成了电路版图并通过了DRC和L...
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